2023年12月24日发(作者：)

#define RALINK_GDMA_BASE 0xB0002800

#define RALINK_AES_ENGINE_BASE 0xB0004000

#define RALINK_FRAME_ENGINE_BASE 0xB0100000

#define RALINK_PPE_BASE 0xB0100C00

#define RALINK_ETH_SW_BASE 0xB0110000

#define RALINK_USB_DEV_BASE 0xB0120000

#define RALINK_MSDC_BASE 0xB0130000

#define RALINK_PCI_BASE 0xB0140000

#define RALINK_11N_MAC_BASE 0xB0180000

#define RALINK_USB_HOST_BASE 0x101C0000#define RALINK_MCNT_CFG 0xB0000500

#define RALINK_COMPARE 0xB0000504

#define RALINK_COUNT 0xB0000508//Interrupt Controller

#define RALINK_INTCTL_SYSCTL (1<<0)

#define RALINK_INTCTL_TIMER0 (1<<1)

#define RALINK_INTCTL_WDTIMER (1<<2)

#define RALINK_INTCTL_ILL_ACCESS (1<<3)

#define RALINK_INTCTL_PCM (1<<4)

#define RALINK_INTCTL_UART (1<<5)

#define RALINK_INTCTL_PIO (1<<6)

#define RALINK_INTCTL_DMA (1<<7)

#define RALINK_INTCTL_PC (1<<9)

#define RALINK_INTCTL_I2S (1<<10)

#define RALINK_INTCTL_SPI (1<<11)

#define RALINK_INTCTL_UARTLITE (1<<12)

#define RALINK_INTCTL_CRYPTO (1<<13)

#define RALINK_INTCTL_ESW (1<<17)

#define RALINK_INTCTL_UHST (1<<18)

#define RALINK_INTCTL_UDEV (1<<19)

#define RALINK_INTCTL_GLOBAL (1<<31)//Reset Control Register

#define RALINK_SYS_RST (1<<0)

#define RALINK_TIMER_RST (1<<8)

#define RALINK_INTC_RST (1<<9)

#define RALINK_MC_RST (1<<10)

#define RALINK_PCM_RST (1<<11)

#define RALINK_UART_RST (1<<12)

#define RALINK_PIO_RST (1<<13)

#define RALINK_DMA_RST (1<<14)

#define RALINK_I2C_RST (1<<16)

#define RALINK_I2S_RST (1<<17)

#define RALINK_SPI_RST (1<<18)

#define RALINK_UARTL_RST (1<<19)

#define RALINK_FE_RST (1<<21)

#define RALINK_UHST_RST (1<<22)

#define RALINK_ESW_RST (1<<23)

#define RALINK_EPHY_RST (1<<24)

#define RALINK_UDEV_RST (1<<25)

#define RALINK_PCIE0_RST (1<<26)

#define RALINK_PCIE1_RST (1<<27)

#define RALINK_MIPS_CNT_RST (1<<28)

#define RALINK_CRYPTO_RST (1<<29)