2024年1月25日发(作者：)

SERIAL PRESENCE DETECTM470T5663QZ3-CE7/CF7/CE6/CD5/CCCOrganization:256M x 64Composition:128M x 8 * 16eaUsed component part #:K4T1G084QQ-HCE7/F7/E6/D5/CC# of rows in module:2 Row# of banks in component:8 banksFeature:30mm height & double sided componentRefresh:8K/64msBin Sort:E7(DDR2-800@CL=5), F7(DDR2-800@CL=6), E6(DDR2-667@CL=5), D5(DDR2-533@CL=4), CC(DDR2-400@CL=3)Contents :

Byte #682936Function described# of Serial PD Bytes written during module productionTotal Number of SPD memory deviceFundameatal memory type# of row address on this assembly# of column address on this assembly# of module rows on this assemblyData width of this assemblyReservedVoltage interface level of this assemblyDDR2 SDRAM cycle time at Max. Supported CAS latency=XDDR2 SDRAM Access time from clock at CL=XDIMM configuration type (address&command parity, data parity,ECC)Refresh ratePrimary DDR2 SDRAM widthError checking DDR2 SDRAM data widthReservedDDR2 SDRAM device attributes : Burst lengths supportedDDR2 SDRAM device attributes : # of banks on each DDR2 SDRAMdeviceDDR2 SDRAM device attributes : CAS latency supportedDIMM Mechanical CharacteristicsDIMM type informationDDR2 SDRAM module attributesDDR2 SDRAM device attributes : GeneralDDR2 SDRAM cycle time at CL= X-1DDR2 SDRAM access time from clock at CL= X-1DDR2 SDRAM cycle time at CL= X-2DDR2 SDRAM access time from clock at CL= X-2Minimum row precharge time(=tRP)Minimum row active to row active delay(=tRRD)Minimum RAS to CAS delay(=tRCD)Minimum active precharge time(=tRAS)

Module rank densityCommand and address setup time before clock(=tIS)Command and address hold time after clock(=tIH)Data input setup time before strobe(=tDS)Data input hold time after strobe(=tDH)Write recovery time(=tWR)Function SupportedCE7CF7CE6128bytes256bytes(2k bit)DDR2 SDRAM14102 Row, Planar, 30.0mm64bits-SSTL 1.8V2.5ns+/-0.40ns3.0ns3.75ns5.0ns+/-0.6ns25h40hHex ValueCCCCE7CF7CE680h08h08h0Eh0Ah61h40h00h05h30h45h00h82h08h00h00h0Ch08h3Dh50h50h60hCD5CD5CCCNote12+/-0.45ns+/-0.5nsNon parity/ECC7.8usx8N/A-4,88 banks3,45,4,36,5,4X =< 3.80SODIMM5,4,338h70h01h04h00h07h38hAnalysis probe not installed, FET switchexternal not enableSupports weak driver, 50Ohm ODT, PASR3.75ns+/-0.5ns5.0ns+/-0.6ns12.5ns3.0ns+/- 0.45ns3.75ns+/-0.5ns15ns7.5ns12.5ns15ns45ns1GB0.175ns0.25ns0.05ns0.125ns0.20ns0.27ns0.10ns0.17ns15ns0.22ns0.25ns0.37ns0.35ns0.47ns0.15ns0.27ns17h25h05h12h40ns32h3.75ns+/-0.5ns5.0ns+/-0.6ns5.0ns+/-0.6ns3Dh50h50h60h32h3Dh50h30h45h3Dh50h50h60h3Ch1Eh3Ch50h60h332Dh01h20h27h25h37h10h17h3Ch22h28h35h47h15h27h3AUG. 2007

SERIAL PRESENCE DETECTByte #3738394647~484950~6162636465~7777879868788899~9899~127128~255Note :Function describedInternal write to read command delay(=tWTR)Internal read to precharge command delay(=tRTP)Memory analysis probe characteristicsExtension of Byte41 tRC and Byte42 tRFCDDR2 SDRAM device min. active to active/auto refresh time(=tRC)DDR2 SDRAM device min. auto-refresh to active/auto-refreshcommand period(=tRFC)DDR2 SDRAM device max. device cycle time(=tCK max)DDR2 SDRAM device max. skew for DQS and associated DQsignals(=tDQSQ max)DDR2 SDRAM read data hold skew factor(=tQHS)PLL Relock TimeDT in SPDHigh Temp. Self RefreshIDD in SPDSPD data revision codeChecksum for Bytes 0 ~ 62Manufacturer JEDEC Manufacturer JEDEC ID code

Manufacturing locationManufacturer Part #(Memory module)Manufacturer part # (DIMM configuration)Manufacturer part # (Data bits & Module type)......Manufacturer part # (Data bits & Module type)

......Manufacturer part # (Data bits & Module type)

Manufacturer part # (Operating Voltage)Manufacturer part # (Module depth)Manufacturer part # (Module depth)Manufacturer Part # (Refresh. # of rows in comp. & interface)

Manufacturer part # (composition component)

Manufacturer part # (Component revision)

Manufacturer part # (Package type)

Manufacturer part # (PCB revision)

Manufacturer part # (Hyphen)

Manufacturer part # (Power)

Manufacturer part # (Minimum cycle time)Manufacturer part # (Minimum cycle time)

Manufacturer part # (T.B.D)

Manufacturer Revision Code(For PCB)

Manufacturer Revision Code (For component)Manufacturing Date (Year)Manufacturing date (week)

Assembly serial #Manufacturer specific data(may be used in future)Open for customer will typically be programmed as 128 will typically be programmed as 256 Bytes.

DatasheetFunction SupportedCE7CF7CE67.5ns7.5ns-tRFC(127.5ns)+tRC(57.5ns)tRFC(127.5ns)57.5ns60ns127.5ns8ns0.20ns0.3ns0.24ns0.34ns--support-Revision 1.2-SamsungSamsungOnyang KoreaM4Blank70T5663Q-dieZ3"-"CE7FE6Blank3Q-die---UndefinedUndefinedD5CC45h02h0.3ns0.4ns0.35ns0.45ns14h1Eh55ns36h39hHex ValueCCC10.0nsCD5CE7CF7CE61Eh1Eh00h06h3Ch7Fh80h18h22h00h00h03h00h12hCD5CCC28hNote3337h31Eh28h23h2DhE6h1ChCEh00h01h4Dh34h20h37h30h54h35h36h36h33h51h5 order bit is Self Refresh "flag". If set to "1", the assembly supports self bytes are programmed by code of Date Year & Date Week with BCD format

bytes are Undefined and can be used for Samsung's own purposeAUG. 2007