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Page 1 Friday, October 3, 2003 9:48 PM1Chapter 11 Problem SetChapter 11PROBLEMS1.[E, None, 11.6] For this problem you are given a cell library consisting of full adders and two-input Boolean logic gates (i.e. AND, OR, INVERT, etc.). an N-bit two's complement subtracter using a minimal number of Boolean logicgates. The result of this process should be a diagram in the spirit of Figure 11.5 . Specifythe value of any required additional signals (e.g., Cin).s the delay of your design as a function of N, t(t, tcarry, tsum, and the Boolean gate delaysandor, tinv, etc.).2.[M, None, 11.6] A magnitude comparator for unsigned numbers can be constructed using fulladders and Boolean logic gates as building blocks. For this problem you are given a celllibrary consisting of full adders and arbitrary fan-in logic gates (i.e., AND, OR, INVERTER,etc.). an N-bit magnitude comparator with outputs and A≥BA = B using a minimalnumber of Boolean logic gates. The result of this process should be a diagram in the spiritof Figure 11.5. Specify the value of any required control signals (e.g., Cin).s the delay of your design in computing the two outputs as a function of N, tttcarry,sum, and the Boolean gate delays (and, tor, tinv, etc.).3.3.[E, None, 11.6] Show how the arithmetic module in Figure 0.1 can be used as a an expression for its propagation delay as a function of the number of bjcjcj+1djdj+1c0c1c1c2c2c3c3c4d0d1d1d2d2d3d3d4a0b0a1b1a2b2a3b3Figure 0.1Arithmetic module.4.[E, None, 11.6] The circuit of Figure 11.2 implements a 1-bit datapath function in dynamic(precharge/evaluate) down the Boolean expressions for outputs F and G. On which clock phases are out-puts F and G valid? what datapath function could this unit be most directly applied (e.g., addition, subtrac-tion, comparison, shifting)?5.[M, None, 11.3] Consider the dynamic logic circuit of Figure 0.2 . is the purpose of transistor Mwith reducing capacitive loading on the clock

1? Is there another way to achieve the same effect, butΦ?

Page 2 Friday, October 3, 2003 9:48 PM2Chapter 11 Problem SetABABCinAAM1BCinBCinGΦΦFFigure 0.2Datapath module can the evaluation phase of F be sped up by rearranging transistors? No transistorsshould be added, deleted, or the evaluation of G be sped up in the same manner? Why or why not?6.[M, SPICE, 11.3] The adder circuit of Figure 0.3 makes extensive use of the transmissiongate XOR. VDD = 2.5 n how this gate operates. Derive the logic expression for the various circuit is this a good adder circuit? a first-order approximation of the capacitance on the Co-node in equivalent gate-capacitances. Assume that gate and diffusion capacitances are approximately e your result with the circuit of Figure 11-6 . that all transistors with the exception of those on the carry path are minimum-size. Use 4/0.25 NMOS and 8/0.25 PMOS devices on the carry-path. Using SPICE simu-lation, derive a value for all important delays (input-to-carry, carry-to-carry, carry-to-sum).VDDBVDDVDDPBBAPAPPCBiSignal setupPVCDDoPPACiSCiPPFigure 0.3Quasi-clocked adder generationCarry generation

Page 3 Friday, October 3, 2003 9:48 PMDigital Integrated Circuits - 2nd Ed37.[M, None, 11.3] The dynamic implementation of the 4-bit carry-lookahead circuitry from Fig.11-21 can significantly reduce the required transistor a domino-logic implementation of Eq. 11.17 . Compare the transistor counts of thetwo is the worst-case propagation delay path through this new circuit? there any charge-sharing problems associated with your design? If so, modify yourdesign to alleviate these effects.8.[C, None, 11.3] Figure 0.4 shows a popular adder structure called the conditional-sum 0.4.a shows a four-bit instance of the adder, while 0.4.b gives the schematics of thebasic adder cell. Notice that only pass-transistors are used in this Boolean descriptions for the four outputs of the one-bit conditional adder on the results of describe how the schematic of 0.4.a results in an an expression for the propagation delay of the adder as a function of the number ofbits N. You may assume that a switch has a constant resistance Ron when active and thateach switch is identical in size.B3A3B2A2B1A1B0A0ConditionalConditionalConditionalConditionalCellCellCellCellC1C0S1S0C1C0S1S0C1C0S1S0C1C0S1S0CoutS3S2S1S0(a) Four-bit conditional-sum adderAAAABBBBAAABS0ABS1C0AC1AAAAAABBA(b) Conditional adder cellFigure 0.4Conditional-sum adder.9.[M, None, 11.3] Consider replacing all of the NMOS evaluate transistors in a dynamicManchester carry chain with a single common pull-down as shown in Fgure 0.5.a. Assumethat each NMOS transistor has (W/L)N = 0.5/0.25 and each PMOS has (W/L)P = 0.75/r assume that parasitic capacitances can be modeled by a 10 fF capacitor on each of the

Page 4 Friday, October 3, 2003 9:48 PM4Chapter 11 Problem Setinternal nodes: A, B, C, D, E, and F. Assume all transistors can be modeled as linear resistorswith an on-resistance, Ron = 5 kΩ. this variation perform the same function as the original Manchester carry chain?Explain why or why ng that all inputs are allowed only a single zero-to-one transition during evalua-tion, will this design involve charge-sharing difficulties? Justify your te the waveforms in Figure 0.5b for P0 = P1 = P2 = P3 = 2.5 V and G0 = G1 = G2 =G3 = 0 V. Compute and indicate tpHL values for nodes A, E, and F. Compute and indicatewhen the 90% precharge levels are φφ1458t(nsec)P0P1P2PCin3ABCDEACinG0G1G2G3FEφF(a) Circuit schematic(b) Partial waveformsFigure 0.5Alternative dynamic Manchester carry-chain adder.10.[M, None, 11.3] Consider the two implementations of Manchester carry gates in Figure e the delay per segment of the two e the layout complexities of the two gates using stick the precharged Manchester carry chain using the gate from b. find the probability thatthe carry signal is propagated from the 15th to the 16th bit of a 32-bit adder, assuming ran-dom inputs.11.[C, None, 11.3] Consider the Radix-4 and Radix-2 Kogge-Stone adders from Figures 11-22and 11-27 extended to 64-bits. All gates are implemented in domino and all gates in a stagehave the same size. The adders have an overall fanout (electrical effort) of logical effort, identify the critical the gates for minimum delay (hint: don't forget to factor in branching). Which adderis faster?'s now consider sparse versions of each of the above trees. In a tree with a sparseness of2, only every other carry is computed and it is used to select 2 sums. Similarly, a tree witha sparseness of 4 computes every fourth carry - and that carry signal is used to select 4sums. Repeat a. and b. for Radix-2 and Radix-4 trees with sparseness of 2 and 4 and com-pare their speed. Which adder is fastest?e the switching power of all adders analyzed in this problem.12.[C, None, 11.3] In this problem we will analyze a carry-lookahead adder proposed by H. Lingmore than 20 years ago, but still among the fastest adders available. In a conventional adder,in order to add two numbersA = an−1n−2n−12 + an−22 + .... + a020B = bn−1n−2n−12 + bn−22 + .... + b020we first compute the local carry generate and propagate terms:

Page 5 Friday, October 3, 2003 9:48 PMDigital Integrated Circuits - 2nd Ed5gi = aibipthen, with a ripple or a tree circuit we form the global carry-out terms resulting from thei = ai + birecurrence relation:Gi = gi + piGi−1

Finally, we form the sum of A and B using local expressions:Si=pi⊕Gi–1In the conventional adder, the terms Gi have, as described, a physical significance. However,an arbitrary function could be propagated, as long as sum terms could be derived. Ling'sapproach is to replace Gi with:Hi = Gi + Gi.e. Hi−1i is true if "something happens at bit i" - there is a carry out or a carry in. Hi

is so-called"Ling's pseudo-carry". that:Hi = gi + tpi−1Hi−1

where

i = ai + bi (it was Ling’s idea to change the notation). a formula for computing the sum out of the operands and Ling's the recursions for Gi and Hi for i = 3. You should get the expressions fpr G3 and H3as a function of the bits of input operands. Simplify the expressions as much as ent the two functions using n-type dynamic gates. Draw the two gates and size thetransistors. Which one helps us build a faster adder? Explain your answer.13.[M, None, 11.4] An array multiplier consists of rows of adders, each producing partial sumsthat are subsequently fed to the next adder row. In this problem, we consider the effects ofpipelining such a multiplier by inserting registers between the adder Figure 11-31 by inserting word-level pipeline registers as required to achievemaximal benefit to throughput for the 4x4 multiplier. Hint: you must use additional regis-ters to keep the input bits synchronized to the appropriate partial for a carry-save, as opposed to ripple-carry, each of the two multiplier architectures, compare the critical path, throughput, andlatency of the pipelined and nonpipelined architecture is better suited to pipelining, and how does the choice of a vector-merging adder affect this decision?14.[M, None, 11.4] Estimate the delay of a 16x16 Wallace tree multiplier with the final adderimplemented using a Radix-4 tree. One FA has a delay of tp, a HA 2/3*tp and a CLA stage½*tp.15.[E, None, 11.5] The layout of shifters is dominated by the number of wires running through acell. For both the barrel shifter and the logarithmic shifter, estimate the width of a shifter cellas a function of the maximum shift-width M and the metal pitch p.16.[E, None, 11.7] Consider the circuit from Figure 0.7 . Modules A and B have a delay of 10 nsand 32 ns at 2.5V, and switch 15 pF and 56 pF respectively. The register has a delay of 2 nsand switches 0.1 pF. Adding a pipeline register allows for reduction of the supply voltagewhile maintaining throughput. How much power can be saved this way? Delay with respectto VDD can be approximated from Figure 11-57.17.[E, None, 11.7] Repeat Problem 16, using parallelism instead of pipelining. Assume that a 2-to-1 multiplexer has a delay of 4 ns at 2.5 V and switches 0.3 pF. Try parallelism levels of 2and by 4. Which one is preferred?

Page 6 Friday, October 3, 2003 9:48 PM6Chapter 11 Problem SetrrInetetssOutigiegeRABRFigure 0.6Pipelined PROBLEMUsing the 0.25 µm CMOS technology, design a static 32-bit adder, with the fol-lowing constraints: capacitance on each bit is limited to not more than bit is loaded with a carry lookahead tree of your choice for implementation. The goal is toachieve the shortest propagation ine the logic design of the adder and W and L of all lly size the design using the method of logical effort. Estimate the capaci-tance of carry signal wires based on the floorplan. Verify and optimize thedesign using SPICE. Compute also the energy consumed per transition. If youhave a layout editor available, perform the physical design, extract the real cir-cuit parameters, and compare the simulated results with the ones obtained ear-lier. For implementation use the 144λ.bit-slice pitch, that corresponds to 36metal-1 tracks. Use metal 1 for cell-level power distrbution and intra-cell rout-ing, metal-2 for short interconnect and metal-3 and metal-4 for long carries.