2024年2月20日发(作者：)

Chapter 5:Clock Networks and PLLs in Arria II DevicesClock Networks in ArriaII DevicesTable5–12 lists the mapping between the input clock pins, PLL counter outputs, and

clock control block 5–g Between Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs for Arria II

DevicesClock Control Block Inputsinclk[0], inclk[1](1)DescriptionCan be fed by any of the four dedicated clock pins on the same side.■inclk[2]

■For ArriaII GX device—can be fed by PLL counters C0 and C2 from the two corner PLLson the same Arria II GZ device—can be fed by PLL counters C0 and C2 from the two center PLLson the same ArriaII GX device—can be fed by PLL counters C1 and C3 from the two corner PLLson the same Arria II GZ device—can be fed by PLL counters C1 and C3 from the two center PLLson the same side.■inclk[3]

■Note to Table5–12:(1)The left side of the ArriaII GX device only allows PLL counter outputs as the dynamic clock source selection to the GCLK network. Therefore,

inclk[0] can be fed by PLL counters C4 or C6, while inclk[1] can only be fed by PLL counter C5.1When combining the PLL outputs and clock pins in the same clock control block,

ensure that these clock sources are implemented on the same side of the device.

For all possible legal

inclk sources for each GCLK and RCLK network, refer to

Table5–2 on page5–12 through Table5–10 on page5– can statically control the clock source selection for the RCLK select block with

configuration bit settings in the configuration file generated by the QuartusII

can power down the ArriaII clock networks both statically and dynamically.

When a clock network is powered down, all the logic fed by the clock network is in an

off-state, thereby reducing the overall power consumption of the device. The unused

GCLK and RCLK networks are automatically powered down through configuration

bit settings in the configuration file generated by the QuartusII software. The

dynamic clock enable or disable feature allows the internal logic to control power-up

or power-down synchronously on GCLK and RCLK networks. This function is

independent of the PLL and is applied directly on the clock network, as shown in

Figure5–12 on page5–16 through Figure5–14 on page5– can set the input clock sources and the

clkena signals for the GCLK and RCLK

clock network multiplexers through the QuartusII software with the ALTCLKCTRL

megafunction. You can also enable or disable the dedicated external clock output pins

with the ALTCLKCTRL megafunction.1When you use the ALTCLKCTRL megafunction to implement dynamic clock source

selection in ArriaII devices, the inputs from the clock pins, except for the left side of

the ArriaIIGX device, feed the

inclk[0..1] ports of the multiplexer, and the PLL

outputs feed the

inclk[2..3] ports. You can choose from among these inputs with the

CLKSELECT[1..0]signal. For the connections between the PLL counter outputs to the

clock control block, refer to Table5–12 on page5– II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 5:Clock Networks and PLLs in Arria II DevicesClock Networks in ArriaII DevicesTable5– Outputs From the PLL Clock Outputs for Arria II GZ Device(Part 2 of 2)PLL NumberClock ResourceL2RCLK[32..43]RCLK[44..63]——L3——B1——B2——R2v—R3v—T1—vT2—vClock Control BlockEvery GCLK and RCLK network has its own clock control block. The control block

provides the following features:■■■Clock source selection (dynamic selection for GCLKs)GCLK multiplexingClock power down (static or dynamic clock enable or disable)Figure5–12 shows the GCLK select blocks for ArriaII devices.

Figure5– Control Block for Arria II DevicesCLKPinPLL CounterOutputs (3)CLKSELECT[1..0](1)222CLKPinInter-TransceiverBlock Clock Lines(4)InternalLogicStatic ClockSelect (2)This multiplexersupports user-controllabledynamic switchingEnable/DisableInternalLogicGCLKNotes to Figure5–12:(1)You can only dynamically control these clock select signals through internal logic when the device is operating in user

mode.(2)These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamicallycontrolled during user mode operation.(3)The left side of the ArriaII GX device only allows PLL counter outputs as the dynamic clock source selection to the

GCLK network.(4)This is only available on the left side of the ArriaII GX the clock source for the GCLK control block either statically with a setting in the

QuartusII software or dynamically with an internal logic to drive the multiplexer

select inputs. When selecting the clock source dynamically, you can either select two

PLL outputs (such as

C0 or C1), or a combination of clock pins or PLL II Device Handbook Volume 1: Device Interfaces and Integration