2024年3月23日发(作者：)
Features
•
High-performance, Low-power AVR
®
8-bit Microcontroller
•
Advanced RISC Architecture
–133 Powerful Instructions – Most Single Clock Cycle Execution
–32 x 8 General Purpose Working Registers + Peripheral Control Registers
–Fully Static Operation
–Up to 16 MIPS Throughput at 16 MHz
–On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
–128K Bytes of In-System Reprogrammable Flash
Endurance: 1,000 Write/Erase Cycles
–Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
–4K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
–4K Bytes Internal SRAM
–Up to 64K Bytes Optional External Memory Space
–Programming Lock for Software Security
–SPI Interface for In-System Programming
JTAG (IEEE std. 1149.1 Compliant) Interface
–Boundary-scan Capabilities According to the JTAG Standard
–Extensive On-chip Debug Support
–Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
Peripheral Features
–Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
–Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
Capture Mode
–Real Time Counter with Separate Oscillator
–Two 8-bit PWM Channels
–6 PWM Channels with Programmable Resolution from 1 to 16 Bits
–8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain (1x, 10x, 200x)
–Byte-oriented 2-wire Serial Interface
–Dual Programmable Serial USARTs
–Master/Slave SPI Serial Interface
–Programmable Watchdog Timer with On-chip Oscillator
–On-chip Analog Comparator
Special Microcontroller Features
–Power-on Reset and Programmable Brown-out Detection
–Internal Calibrated RC Oscillator
–External and Internal Interrupt Sources
–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
–Software Selectable Clock Frequency
–ATmega103 Compatibility Mode Selected by a Fuse
–Global Pull-up Disable
I/O and Packages
–53 Programmable I/O Lines
–64-lead TQFP
Operating Voltages
–2.7 - 5.5V (ATmega128L)
–4.5 - 5.5V (ATmega128)
Speed Grades
–0 - 8 MHz (ATmega128L)
–0 - 16 MHz (ATmega128)
•
•
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Preliminary
Summary
•
•
•
•
•
Rev. 2467AS-08/01
Note: This is a summary document. A complete document is
available on our web site at .
1
Pin Configurations
Figure 1. Pinout ATmega128
A
V
C
C
G
N
D
A
R
E
F
P
F
0
(
A
D
C
0
)
P
F
1
(
A
D
C
1
)
P
F
2
(
A
D
C
2
)
P
F
3
(
A
D
C
3
)
P
F
4
(
A
D
C
4
/
T
C
K
)
P
F
5
(
A
D
C
5
/
T
M
S
)
P
F
6
(
A
D
C
6
/
T
D
O
)
P
F
7
(
A
D
C
7
/
T
D
I
)
G
N
D
V
C
C
P
A
0
(
A
D
0
)
P
A
1
(
A
D
1
)
P
A
2
(
A
D
2
)
Overview
The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the sys-
tem designer to optimize power consumption versus processing speed.
2
ATmega128(L)
2467AS–08/01
(
O
C
2
/
O
C
1
C
)
P
B
7
T
O
S
C
2
/
P
G
3
T
O
S
C
1
/
1
P
G
4
R
E
S
E
T
V
C
C
G
N
D
X
T
A
L
2
X
T
A
L
1
(
S
C
L
/
I
N
T
0
)
P
D
0
(
S
D
A
/
I
N
T
1
)
P
D
1
(
R
X
D
1
/
I
N
T
2
)
P
D
2
(
T
X
D
1
/
I
N
T
3
)
P
D
3
(
I
C
1
)
P
D
4
(
X
C
K
1
)
P
D
5
(
T
1
)
P
D
6
(
T
2
)
P
D
7
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
PEN
RXD0/(PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(IC3/INT7) PE7
(SS) PB0
(SCK) PB1
(MOSI) PB2
(MISO) PB3
(OC0) PB4
(OC1A) PB5
(OC1B) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6
4
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2(ALE)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PG1(RD)
PG0(WR)
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