2024年4月1日发(作者：)

一、TMAX的使用

1. 工具接口

Basic input of TetraMAX to perform ATPG are the vendor gate-level simulation

libraries, design netlist, command script and test procedure file. Main output data are

the test patterns and reports on results. In order to read in netlist and library files, use

the “read netlist” command or the Netlist button of the GUI. The netlist format

(Verilog, EDIF, VHDL) is automatically detected. It is recommended you use Verilog

as the netlist input format. TetraMAX also automatically detects netlist compression

(none, GZIP, proprietary binary). A single file may contain one or more modules. By

using multiple files, mixed language netlists are supported. A single read command

may use wildcards to match multiple files using the „?‟ and „*‟ characters.

Example:

read netlist /proj/mars/lander/shared/*/??DFF*.v

There is no restriction whether to use flat or hierarchical netlists.

Standards for pattern input: VCD-E, WGL, STIL.

Standards for pattern output: Verilog, WGL, STIL, VHDL.

Multiple pattern compression techniques (static & dynamic).

Built-in GZIP compression support for file inputs and outputs (designs, libraries,

protocols, patterns, fault lists).

2. 使用流程

The diagram illustrates the basic test pattern generation flow. The three operation

modes of TetraMAX are shown by different colors. During build mode the design and

libraries are read in, and the ATPG model of the design is built. If the build step was

successful, you automatically get into DRC (design rules checking) mode. Here you

specify all information needed by the tool to configure the design for test. The test

procedure file (STIL = Standard Test Interface Language) is read in. If DRC was

successful, you get into Test mode. You finally adjust settings for ATPG, start pattern

generation, perform pattern compression and save the patterns to disk.

STEP:

(1) Reading the Library Files

Use NETLIST button or read netlist command: BUILD> read netlist mylibrary.v

Read netlists in hierarchy order, from library leaf cells (first) to top level module (last).

Example:BUILD> read netlist /libs/0.18u/*/??DFF*.v

In case of duplication when reading in netlists, the default behavior is to keep the last

module definition encountered. Netlist type (Verilog, EDIF, VHDL) is automatically

detected. Netlist compression (none, GZIP, proprietary binary) is automatically

detected. A single file may have one or more modules. A single read command may

use wildcards to match multiple files using the „?‟ and „*‟ characters.

(2) Read Design Netlist

Use NETLIST button or read netlist command:BUILD> read netlist my_asic.v

Designs may be described using forms of: