2024年6月9日发(作者：)

Pin

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

TRST

+12V

TMS

TDI

+5V

INTA

INTC

+5V

+5V

+3.3V

Universal

Test Logic Reset

+12 VDC

Test Mde Select

Test Data Input

+5 VDC

Interrupt A

Interrupt C

+5 VDC

Reserved VDC

+V I/O (+5 V or +3.3 V)

Reserved VDC

Ground or Open (Key)

Ground or Open (Key)

Reserved VDC

Reset

+V I/O (+5 V or +3.3 V)

Grant PCI use

Ground

Reserved VDC

Address/Data 30

+3.3 VDC

Address/Data 28

Address/Data 26

Ground

Address/Data 24

Initialization Device Select

+3.3 VDC

Address/Data 22

Address/Data 20

Ground

Address/Data 18

Address/Data 16

+3.3 VDC

Address or Data phase

Ground

Description

RESV01

+5V

RESV03

GND03

GND05

RESV05

RESET

+5V

GNT

GND08

RESV06

AD30

+3.3V01

AD28

AD26

GND10

AD24

IDSEL

+3.3V03

AD22

AD20

GND12

AD18

AD16

+3.3V05

FRAME

GND14

+3.3V

(OPEN)

(OPEN)

+3.3V

Signal Rail

(OPEN)

(OPEN)

Signal Rail

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

TRDY

GND15

STOP

+3.3V07

SDONE

SBO

GND17

PAR

AD15

+3.3V10

AD13

AD11

GND19

AD9

C/BE0

+3.3V11

AD6

AD4

GND21

AD2

AD0

+5V

REQ64

VCC11

VCC13

GND

C/BE[7]#

C/BE[5]#

+5V

PAR64

AD62

GND

AD60

AD58

GND

+3.3V

+3.3V

Signal Rail

Signal Rail

Target Ready

Ground

Stop Transfer Cycle

+3.3 VDC

Snoop Done

Snoop Backoff

Ground

Parity

Address/Data 15

+3.3 VDC

Address/Data 13

Address/Data 11

Ground

Address/Data 9

Command, Byte Enable 0

+3.3 VDC

Address/Data 6

Address/Data 4

Ground

Address/Data 2

Address/Data 0

+V I/O (+5 V or +3.3 V)

Request 64 bit ???

+5 VDC

+5 VDC

Ground

Command, Byte Enable 7

Command, Byte Enable 5

+V I/O (+5 V or +3.3 V)

Parity 64 ???

Address/Data 62

Ground

Address/Data 60

Address/Data 58

Ground