2024年6月14日发(作者：)
Verilog常见必备面试题
1、Use verilog hdl to implement a flip-flop with synchronous
RESET and SET, a Flip-flop with asynchronous RESET and SET.
always@(posedge clk or negedge reset always@(posedge clk)
or posedge set)
begin
begin
if(set)
if(set)
Q<>
Q<>
else if(!reset)
else if(!reset)
Q<>
Q<>
else
else
Q<>
Q<>
end
end
异步reset和set 同步reset和set
2、Use verilog hdl to implement a latch with asynchronous
RESET and SET.
always @(clk or reset or set)
begin
if(set)
Q=1;
else if(!reset)
Q=0;
else
Q=D;
end
3、Use Verilog hdl to implement a 2-to-1multiplexer.
assign Y=(SEL==1'b0)?A:B;
4、Use AND gate, OR gate and Inverter toimplement a 2-to-
1 multiplexer.
module MUX21(A, B, SEL, Y);
input A,B,SEL;
output Y;
net SEL_NOT, A_AND, B_AND;
not u0(SEL_NOT, SEL);
and u1(A_AND, SEL_NOT, A);
and u2(B_AND, SEL, B);
or u3(Y, A_AND, B_AND);
endmodule
5、Use a 2-to-1 multiplexer to implement a two input OR
gate.
module or2(A, B, Y);
input A, B;
output Y;
MUX21 u0(Y, A, B, B );
endmodule
module MUX21(Y, A ,B, SEL)
input A,B,SEL;
output Y;
assign Y=(SEL==1’b0):A:B;
endmodule
assign Y=A?A:B;
6、Use a tri-state buffer to implement Open-Drain buffer.
assign Y=EN?DataIn:1'bz;
7、To divide one input clock by3, Written by verilog hdl.
module clk_div_3(clk, reset, clk_out);
input reset,clk;
output clk_out;
reg clk_out;
reg [1:0] cnt;
always@(posedge clk or negedge reset)
begin
if(!reset)
begin cnt<>
clk_out<>
else if(cnt==2'b01) begin clk_out<>
cnt<=cnt+1'b1;>=cnt+1'b1;>
else if(cnt==2'b10) begin clk_out<>
cnt<>
else cnt<>
end
endmodule
， 占空比1/3
8、To divide one input clock by3, 50% dutycycle is required.
Written by verilog hdl.
module clk_div_3(clk, reset, clk_out);
input reset,clk;
output clk_out;
reg clk_out1, clk_out2;
reg [1:0] cnt1,cnt2;
assign clk_out = clk_out1 | clk_out2;
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