2023年11月29日发(作者：)

c语⾔中的error和warning,ISE中常见WARNING和ERROR及

其解决⽅法

1."WARNING:Route:455 - CLK Net:trn_clk_OBUF may have excessive skew&nBSP;

because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK

template."

Solution

This message informs the user that some loads on the clock net are not

clock pins. Therefore, the clock template that is normally uSED to connect

clock pins will not be used to connect the loads. A different routing that

involves local routing will be used, potentially inducing some skew on the

clock net.

Opening your design in FPGA Editor will allow you to see what loads are

elements from your HDL description.

starting in ISE 7.1i, Project Navigator has the capability to do message

WARNING:Xst:1426 - The value init of the FF/Latch reg hinders the constant

Verilog

end case;