2024年1月11日发(作者：)

Keil 与Proteus仿真问题总结

1、 Keil与Proteus联调8051单片机的时候，效果相当于添加.hex文件到单片机后运行；Keil下关于off-chip code memory 、off-chip Xdata memory的设置对调试没有任何影响。如下图：

使用了T80C31，内部没有ROM，外部ROM也不设置，同样可以仿真，RAM也一样。

如果选择的是AT89S51，内部ROM只有4K，而编译的程序有6K多，设置如下图示：

就可以仿真运行，不管是Keil自带的Simulator，还是与Proteus联调。

2、 如果Proteus对51单片机的设置如下图示：

Simulate Program Fetches属性选择了Yes，则Keil与Proteus无法联合调试；若选择了No，则不用设置Program Files，Keil与Proteus一样可以联合调试，效果就相当于为Program Files添加了.hex文件一样。

上图示CPU为80C31，内部没有ROM，“{ROM=0} ”，但照样可以添加.hex文件，而且添加的.hex文件大小为6K多。

只要Simulate Program Fetches属性选择了No，则不管电路有没有外部扩展ROM，一样可以仿真运行。

而如果Simulate Program Fetches属性选择了Yes，那么即使外部ROM连接正确，但是不管怎么设置属性EXTROM、EXTRAM、Code memory map、Data memory

map的值，都不能仿真。

如果在Proteus中，外部RAM设置到了8000-FFFF这个地址段，那么需要在程序中指定地址，否则读取不到外部RAM，仿真失败。因此一般把外部RAM的地址分配到0000开始的地址空间。

3、 关于仿真外部程序存储器的问题，主要要了解清楚8051Model的内部构架规则。摘抄英文帮助如下：

By default, all external data memory accesses are fully modelled. That is to say that each

external data memory cycle involves simulating the numerous transitions of ALE and the P0

and P2 port pins. A typically cycle will involve around 50 pin state transitions is thus vastly

expensive in terms of simulation time.

In contrast, all program memory cycles are simulated internal to the 8051 model - that is to

say that the program bytes are looked up in a memory buffer internal to the chip and no

pin-state transitions are simulated. This is the case irrespective of the amount of internal ROM

available on a particular 8051 part, and is done in order to achieve reasonable simulation

speeds. This optimisation can be disabled by specifying:

DBG_FETCH=FALSE

For applications which make extensive use of external data RAM, two further optimisations

can be specified.

DATARAM Property

This specifies regions of the external memory map which can be treated as RAM and

simulated internally to the 8051 model. A typical example would be:

DATARAM=0000-7FFF,C000-FFFF

This would specify two regions of external data memory.

CODERAM Property

Where regions of the external memory map are wired in a Von-Neumann configuration

(external data memory and code memory are the same), this can be specified as follows:

CODERAM=0000-7FFF

Any external memory writes to the region 0000-7FFF will then 'write through' to the internal

program memory buffer of the model and be 'seen' by subsequent instruction fetches and

MOVC instructions.

4、 关于8051Model的所有属性，摘抄如下：

The 8051 model supports the following properties:

Property Default Description

PROGRAM - Specifies one or more program files to be loaded into the model's internal

code memory. The files can be either Intel hex files or OMF51 absolute object module format

files. Use commas to separate multiple file names. See Specifying The Program File for more

information.

CLOCK 1.2MHz Specifies the clock frequency of the processor. For reasons of efficiency,

the clock circuitry is not simulated, and the clock rate of the processor is determined solely by

this value.

DBG_FETCH FALSE If TRUE, causes the model to simulate external program fetches.

This mode of operation is extremely slow, but will allow you to test external program memory

decode circuitry.

DATARAM - Specifies regions of the memory map that correspond to external data

RAM. This allows for much faster simulation of external memory accesses. See Modelling

the Memory Map for more information.

CODERAM - Specifies regions of the external memory map that are shared between

code and data (i.e. von-neumann decoding). See Modelling the Memory Map for more

information.

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