2024年1月11日发(作者：)

Flash ControllerMNL-1100 | 2021.03.0915.4.2. Bootstrap InterfaceThe NAND flash controller provides a bootstrap interface that allows software tooverride the default behavior of the flash controller. The bootstrap interface containsfour bits, which when set appropriately, allows the flash controller to skip theinitialization phase and begin loading from flash memory immediately after thecontroller is reset. These bits are driven by software through the system are sampled by the NAND flash controller when the controller is released d InformationSystem Manager on page 166For more information about the bootstrap interface control bits.15.4.2.1. Bootstrap Setting BitsTable rap Setting BitsBitExample Value for 512-Byte Page1(24)11••1—flash device supports two-cycle addressing0—flash device support three-cycle addressingnoinitpage512noloadb0p0tworowaddrRelated InformationConfiguration by Host on page 19515.4.3. Configuration by HostIf the system manager sets

bootstrap_inhibit_init to 1, the NAND flashcontroller does not perform the process described in "Discovery and Initialization". Inthis case, the host processor must configure the flash performance is not a concern in the design, the timing registers can be leftunprogrammed.15.4.3.1. Recommended Bootstrap Settings for 512-Byte Page DeviceTable ended Bootstrap Settings for an 8-bit, 512-Byte Page DeviceRegister(25)Value10 indicating an 8-bit NAND

devices_connecteddevice_width(24)When this register is set, the NAND flash controller expects the host to program the relateddevice parameter registers. For more information, refer to "Configuration by Host".All registers are in the

config group.(25)Send Feedback

Flash ControllerMNL-1100 | 2021.03.09Register(25)Value1 indicating a single-plane deviceThe value of this register must reflect the flash device’s page mainarea value of this register must reflect the flash device’s page sparearea value of this register must reflect number of pages per block inthe flash _of_planesdevice_main_area_sizedevice_spare_area_sizepages_per_block15.4.4. Local Memory BufferThe NAND flash controller has three FIFO memories implemented using dual-portedSRAM.•••Write FIFO—The read data from the host memory resides in the Write FIFO beforebeing flushed to the FIFO—The data from the device is read and stored in the FIFO before beingforwarded to the host FIFO—This buffer holds data for applying the ECC correction while the logiccomputes error locations and of these memories is protected by ECC, and by interrupts for single and double-bit errors. The ECC block is integrated around a memory wrapper. It provides outputsto notify the system manager when single-bit correctable errors are detected (andcorrected); and when double-bit uncorrectable errors are detected. The ECC logic alsoallows injection of single- and double-bit errors for test purposes. It must be initializedto enable the ECC more information about ECC, refer to the Error Checking and Correction d InformationError Checking and Correction Controller on page 13315.4.5. ClocksThe software enable for NAND is

nand_clk_en and is set to ENABLE by default. Also,during the automatic initialization performed after getting out of reset,

nand_clk_enis active to ensure that all clocks are active if RAM is cleared for security.(25)All registers are in the

config Feedback

Flash ControllerMNL-1100 | 2021.03.09Figure Clocking DiagramClockManagerl4_mp_clkClockGatenand_mp_clknand_mp_clk NANDControllerDivideby 4nand_clkNote: When routing the NAND interface to the FPGA it may be necessary to increase thevalue of

max_rd_delay to compensate for the additional delay between the controllerand the FPGA I/d InformationClock Manager on page 15415.4.5.1. Clock GenerationThe clock manager sends the top level clock from the clock manager sends the 200 MHz clock,

l4_mp_clk, to the NAND FlashController. This clock becomes the NAND reference clock called

nand_mp_clk. Thenand_mp_clk is divided by four and is used for input and output. Since the NANDplaces a 200 MHz limit on the clock, each of these generated clocks are 50 MHz andcalled

nand_clk.15.4.5.2. Clock EnableThe

nand_mp_clk and

nand_clk clocks have enables.15.4.5.3. Clock SwitchingWhen you use clock switching, you must follow the following requirements:•••Ensure that there is no re must disable this module during the frequency switch and re-enable itafter the frequency has clock switching is complete, the software must reconfigure the NANDinitialization registers according to the new frequency before triggering any newtransactions onto the flash interface.15.4.6. ResetsThe NAND flash controller has one external reset signal,

nand_flash_rst_n, thatresets it. Once a reset is initiated, access to the NAND flash controller should not beattempted until after 20

nand_clk :

The minimum reset time for the NAND flash controller is 10

nand_clk clock Feedback