2024年2月3日发(作者：)

调制模块

module two_ASK(clk,reset,x,y);

input clk;

input reset;

input x;

output y;

reg[1:0]cnt;

reg carriers;

always@(posedge clk)begin

if(!reset)begin

cnt<=2'b00;

carriers<=0;

end

else begin

if(cnt==2'b11)begin

cnt<=2'b00;

carriers<=~carriers;

end

else begin

carriers<=carriers;

cnt<=cnt+1;

end

end

end

assign y=x&carriers;

endmodule

解调模块

module Ask_two(clk,reset,x,y);

input clk;

input reset;

input x;

output y;

reg y;

reg[2:0]cnt;

reg[2:0]m;

always@(posedge clk)begin

if(!reset)begin

cnt<=3'b000;

end

else if(cnt==3'b111)

cnt<=3'b000;

else

cnt<=cnt+1;

end

always@(posedge x)begin

if(!reset)begin

m<=3'b000;

end

else begin

if(cnt==3'b110)begin

if(m<=3'b010)

y<=1'b0;

else

y<=1'b1;

m<=3'b000;

end

else

m<=m+1;

end

end

endmodule