2024年3月20日发(作者：)
查询IDT2309供应商
3.3V ZERO DELAY
CLOCK BUFFER
IDT2309
FEATURES:
•Phase-Lock Loop Clock Distribution
•10MHz to 133MHz operating frequency
•Distributes one clock input to one bank of five and one bankd
of four outputs
•Separate output enable for each output bank
•Output Skew < 250ps
•Low jitter <200 ps cycle-to-cycle
•IDT2309-1 for Standard Drive
•IDT2309-1H for High Drive
•No external RC network required
•Operates at 3.3V V
DD
•Available in SOIC and TSSOP packages
DESCRIPTION:
The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2309 is a 16-pin version of the IDT2305. The IDT2309 accepts
one reference input, and drives two banks of four low skew clocks. The
-1H version of this device operates at up to 133MHz frequency and has
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT2309 enters power down, and the outputs are tri-stated. In this mode,
the device will draw less than 25µA.
The IDT2309 is characterized for both Industrial and Commercial
operation.
NOTE: For new designs, refer to AN-233.
FUNCTIONAL BLOCK DIAGRAM
16
CLKOUT
1
REF
PLL
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
S2
S1
8
9
Control
Logic
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
c 2002 Integrated Device Technology, Inc.
NOVEMBER 2002
DSC 5175/5
1
PIN CONFIGURATION
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SOIC/ TSSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
SymbolRating
Supply Voltage Range
Input Voltage Range (REF)
Input Voltage Range
(except REF)
I
IK
(V
I
< 0)
I
O
(V
O
= 0 to V
DD
)
V
DD
or GND
T
A
= 55°C
(in still air)
(3)
T
STG
Operating
Temperature
Operating
Temperature
Storage Temperature Range
Commercial Temperature
Range
Industrial Temperature
Range
-40 to +85°C
–65 to +150
0 to +70
°C
°C
Input Clamp Current
Continuous Output Current
Continuous Current
Maximum Power Dissipation
Max.
–0.5 to +4.6
–0.5 to +5.5
–0.5 to
V
DD
+0.5
–50
±50
±100
0.7
mA
mA
mA
W
Unit
V
V
V
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
V
DD
V
I
(2)
V
I
APPLICATIONS:
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
NOTES:
es greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name
REF
(1)
CLKA1
(2)
CLKA2
(2)
V
DD
GND
CLKB1
(2)
CLKB2
(2)
S2
(3)
S1
(3)
CLKB3
(2)
CLKB4
(2)
CLKA3
(2)
CLKA4
(2)
CLKOUT
(2)
NOTES:
pull down.
pull down on all outputs.
pull ups on these inputs.
Pin Number
1
2
3
4, 13
5, 12
6
7
8
9
10
11
14
15
16
Type
IN
Out
Out
PWR
GND
Out
Out
IN
IN
Out
Out
Out
Out
Out
Functional Description
Input reference clock, 5 Volt tolerant input
Output clock for bank A
Output clock for bank A
3.3V Supply
Ground
Output clock for bank B
Output clock for bank B
Select input Bit 2
Select input Bit 1
Output clock for bank B
Output clock for bank B
Output clock for bank A
Output clock for bank A
Output clock, internal feedback on this pin
2
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