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DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

September 1986

Revised February 2000

DM7473

Dual Master-Slave J-K Flip-Flops

with Clear and Complementary Outputs

General Description

This device contains two independent positive pulse trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flops after a complete clock

pulse. While the clock is LOW the slave is isolated from the

master. On the positive transition of the clock, the data

from the J and K inputs is transferred to the master. While

the clock is HIGH the J and K inputs are disabled. On the

negative transition of the clock, the data from the master is

transferred to the slave. The logic states of the J and K

inputs must not be allowed to change while the clock is

HIGH. Data transfers to the outputs on the falling edge of

the clock pulse. A LOW logic level on the clear input will

reset the outputs regardless of the logic states of the other

inputs.

Ordering Code:

Order Number

DM7473N

Package Number

N14A

Package Description

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection DiagramFunction Table

Inputs

CLR

L

H

H

H

H

CLK

X

J

X

L

H

L

H

K

X

L

L

H

H

Q

L

Q

0

H

L

Toggle

Outputs

Q

H

Q

0

L

H