2024年4月19日发(作者：)

英文资料及中文翻译

One A brief introduction of DDS system

1 the basic principle of DDS

The basic principle is to use DDS sampling theorem, through the querying

method produce waveform. The structure of DDS has a lot of kinds, the basic of the

circuit principle available figure 1-1 to said.

K

Phase Waveform The D/A

Low pass

accumulatmemory

converter filter

Fs

F

O

Figure 1-1 DDS schematic

Phase accumulators by N a adder and N a accumulate registers cascade

composition. Each to a clock pulse fs, adder will frequency control word k and

accumulate registers the accumulation phase output data together and add the results

of data sent to accumulate register input. Accumulate registers adder will last clock

pulse that is produced when the new role of the phase to the adder feedback data input,

so that the adder next clock pulse under the effect of frequency control word to

continue with adding together. So, phase accumulators under the action of the clock,

increasing the frequency control word to linear phase to attack. Can see from this,

phase accumulators in each clock pulse input, the frequency control word accumulate

a, phase accumulators output data is the signal of the synthetic phase, phase

accumulators spillover frequency is the signal frequency DDS output. Using phase

accumulators output data as waveform memory (ROM) of the phase of the sampling

address, so just put the stored in memory of the waveform sampling waveform in

value (binary code) find out by the look-up table, completed phase to amplitude

conversion. The output waveform memory to D/A converter, D/A converter is the

digital quantity of the wave form amplitude convert required amount of frequency

synthesis simulation form signal. Low-pass filter used to filter out do not need to

sample weight, so that the output spectrum pure sine wave signal. DDS in relative

bandwidth, frequency conversion time, high resolution, phase continuity, orthogonal

output and a series of integrated performance indexes far more than the traditional

frequency synthesis technology can reach the level, for the system to provide the

superior performance of simulation signal source.

2 DDS performance characteristics

(1) the output frequency relative bandwidth is wide

Output frequency bandwidth for 50% fs (the theoretical value). But considering

the low-pass filter features and design of difficulty and the output signal stray

suppression, the actual output frequency bandwidth still can reach 40% fs. 

(2) frequency conversion time is short

DDS is a open loop system, without any feedback part, this structure makes DDS

of frequency conversion time is very short. In fact, in the frequency of DDS control

word after the changes required to pass through a clock cycle according to the new

phase after incremental accumulate, can realize frequency conversion. Therefore,

frequency conversion control word frequency is equal to the time of transmission time,

also is a clock cycle time. The clock, the higher the frequency, the transition time is

shorter. The frequency conversion time DDS Dana seconds orders of magnitude, the

frequency of use other than synthetic methods are short several orders of magnitude.

(3) the frequency resolution is extremely high

If the clock frequency of fs changeless, the frequency of DDS by phase

accumulators resolution of the digits N decision. As long as the increase of the phase

accumulators digits N can obtain arbitrarily small frequency resolution. At present,

most of the resolution of the 1 Hz DDS in order of magnitude, many less than 1 MHz

even smaller. 

(4) continuous phase changes

Change DDS output frequency, in fact changed each clock cycle of the phase of

the delta, phase function curve is continuous, just in the frequency of the frequency

change moment happened mutations, so keep the signal phase continuity.

(5) the flexibility of output waveform

As long as the internal and the corresponding control such as DDS FM control

FM, phase-modulation control PM and an AM control AM, that can be flexible to

realize FM, jamming and an AM function, produce FSK, PSK, ASK and MSK signal

etc. In addition, as long as the waveform DDS in memory store different waveforms,

can achieve all kinds of output waveform, such as triangle wave, the sawtooth wave

and rectangular wave even any waveform. When the waveform memory storage DDS

respectively sine and cosine functions table, we can get the two orthogonal way

output.

(6) other advantages

Because in almost all parts of DDS belongs to the digital circuit, easy to

integration, low power consumption, small volume, light weight, high reliability, and

easy to program, use a flexible, so high performance to price ratio.

Two AT89S52 SCM profile

AT89S52 devices for ATMEL by the production of a low power consumption,

high performance CMOS8 a micro controller, and has 8 K in system programmable

Flsah memory.

1 AT89S52 devices main function lists are as follows:

1, have clever 8 bits CPU and in the system programmable Flash

2, the chip with internal clock oscillator (the highest working frequency to

traditional 12 MHz)

3, internal program memory (ROM) for 8 KB

4, internal data memory (RAM) for 256 bytes

5, 32 programmable I/O mouth line

6, 8 interrupt vector source

7, three 16 timer/counter

8, level 3 encryption program memory

9, full-duplex UART serial channel

2 and AT89S52 devices each pin function is introduced:

VCC:

AT89S52 devices power is the input, meet + 5 V.

VSS:

The power to end.

XTAL1:

Single chip system clock of inverse amplifier input terminal.

XTAL2:

The system clock inverse amplifier output terminal, generally in the design as

long as XTAL1 and put the XTAL2 in a quartz crystal oscillation system can action,

in addition to the two pins and to join a 20 PF between the small capacitance, can

make the system more stable, avoid noise interference and crash.

RESET:

AT89S52 devices reset pin, high level action, when to chip reset, as long as this

pin level up to high level and keep two machine cycle more time, AT89S51 and can

finish the various movements of the system reset, make internal special function of

the register contents shall be set to the known condition, and to address 0000 H began

to read in a program code and execution procedures.

EA/Vpp:

"EA" for English "External Access" of the abbreviations, said Access External

program code of Italy, low level action, that is when this pin meet low level, the

system will Access External program code (stored in External EPROM) to execute a

program. So in 8031 and 8032, EA pin must meet low level, because its internal no

program memory space. If is the use of the internal process 8751 space, the pin to

pick up into high level. In addition, the program code in 8751 when the drive to

internal EPROM, can use the pin to input and V burn high pressure (Vpp).

ALE/PROG:

ALE is English "Address Latch Enable" of the abbreviations, said Address

latches Enable signal. AT89S52 devices can use a pin to trigger the external eight

latches (such as 74 LS373), will port 0 address bus (A0-A7) lock into the latches,

because in many ways of AT89S52 work send address and data. At ordinary times in

the program execution ALE the output of the pin frequency is about 1/6 of the

working frequency of the system, and it can be used to drive the other perimeter of the

chip, and the input. In addition the drive in 8751 the program code, the pins will be as

the special programming function to use.

PSEN:

This as "Program Store Enable" abbreviation, its meaning for the Program to

Store opening, when 8051 were set become external Program code read work mode

(EA = 0), will send the signal in order to obtain the Program code, usually the

supporting feet is received EPROM OE the feet. AT89S52 devices can use PSEN and

RD pin existing external opening respectively RAM and EPROM, allow the data

storage and program memory can be combined together and share 64 K addressed

range.

PORT0 (P0.0 ~ P0.7) :

Port 0 is a 8 bits wide Open Drain (Open Drain) two-way I/o port, a total of eight

bit, P0.0 said a 0, P0.1 said a 1, by analogy. The other three I/O port (P1, P2, P3) does

not have this circuit configuration, but internal one ascension circuit, P0 in as I/O only

can push eight the LS TTL load. If when EA pin for low electricity at ordinary times

(i.e. access external program code or data storage), in many ways P0 work provide the

address bus (A0-A7) and the data bus (D0 ~ D7). The designer should be plus latches

will port 0 send out address switch to lock become A0-A7, together with the port 2

send out the A8 ~ A15 to synthesize a complete 16 the address bus, and addressed to

the 64 K external memory space.

PORT2 (P2.0 ~ P2.7) :

Port 2 is a circuit of the internal ascension two-way I/O port, each pin can push

four the LS TTL load, if the port 2 output set to high electricity at ordinary times, this

port can be as input to use. Except as general P2 I/O port use outside, if in the external

expansion program memory AT89S52 or data storage, and provide the address bus

high byte A8 ~ A15, this time P2 cannot as I/O to use.

PORT1 (P1.0 ~ P1.7) :

Port 1 also is to have internal ascension circuit two-way I/O port, the output

buffer can push four LS TTL load, as if the port 1 output set to high level, is this port

to input data. If is to use the 8052 or 8032 words, P1.0 and as the external input pulse