2024年6月14日发(作者：)

Table 1-29:U2 FPGA SMA to Buffered Differential Test Clock Connections (Cont’d)

SMA Differential

Clock Net Names

ICS854S006AGILF U126

1-to-6 Buffer Output Net

Names

U2_TEST_REFCLK3_P

U2_TEST_REFCLK3_N

U2_TEST_REFCLK4_P

U2_TEST_REFCLK4_N

U2_TEST_REFCLK5_P

U2_TEST_REFCLK5_N

ICS8535AGILF

Dual2-to-1

Multiplexer Input

Pin Number

U121.6

U121.7

U122.1

U122.2

U122.6

U122.7

U2 FPGA Test

SMA

U1 and U2 FPGA Si570 with 1-to-6 Clock Buffer (Two Circuits)

See Figure1-2 callout [44].

The U1 FPGA and the U2 FPGA each have an I

2

C programmable Silicon Labs Si570 3.3V

LVDS 10-MHz to 810-MHz oscillator connected to a 1-to-6 ICS854S006AGILF differential

clock buffer (U64–U13 and U65–U18, respectively). Refer to Differential 2.5V Si570 LVDS

Oscillators, page36, for links to further information about the Si570. The six buffer output

pairs are shared between U1 and U2 as shown in Table1-30 and Table1-31. Refer to ML631

Schematic page 15 for U64, and page 69 for U65 [Ref1].

Table 1-30:

U1 FPGA

Si570 U64

U64.4

U64.5

Si570 U64 Driven Additional U1 and U2 Differential Clock Sources

Si570 Differential

Clock Net Names

SI570_4_P

SI570_4_N

ICS854S006AGILF 1-to-6

Buffer Output Net Names

U1_SI570_4_P

U1_SI570_4_N

U2_SI570_4_P

U2_SI570_4_N

U1_MGTREFCLK1_104_P

U1_MGTREFCLK1_104_N

U2_MGTREFCLK1_114_P

U2_MGTREFCLK1_114_N

U1_P1_TX_REFCLK_P

U1_P1_TX_REFCLK_P

U1_P2_TX_REFCLK_P

U1_P2_TX_REFCLK_P

Destination

Pin Number

U1.N12

U1.M12

U2.N11

U2.M10

U1.Y35

U1.Y36

U2.Y10

U2.Y9

P1.A1

P1.B1

P2.A1

P2.B1

ML631 Board User Guide

UG841 (v1.0) March 9, 2012