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ControllerMNL-1100 | 2021.03.09Related Information•••Motorola SPI Protocol on page 419Texas Instruments Synchronous Serial Protocol (SSP) on page 421National Semiconductor Microwire Protocol on page 42119.4.2.1. Serial Bit-Rate Clocks19.4.2.1.1. SPI Master Bit-Rate ClockThe maximum frequency of the SPI master bit-rate clock (sclk_out) is one-half thefrequency of SPI master clock (l4_main_clk). This allows the shift control logic tocapture data on one clock edge of
sclk_out and propagate data on the oppositeedge. The
sclk_out line toggles only when an active transfer is in progress. At allother times it is held in an inactive state, as defined by the serial protocol under whichit operates. †Figure m sclk_out/l4_main_clk RatioCapturel4_main_clkDrive 1Capture 1Drive 2Capture 2Drive 3Capture 3sclk_outtxd/rxdMSBThe frequency of
sclk_out can be derived from the equation below, where
l4_main_clk for both master and slave modules. †Fsclk_out = F
BAUDR, holding any even value in the range 2 to65,534. If SCKDV is 0, then
sclk_out is disabled. †The following equation describes the frequency ratio restrictions between the bit-rateclock
sclk_out and the SPI master peripheral clock. The SPI master peripheral clockmust be at least double the offchip master clock. †Table Master Peripheral ClockSPI Master Peripheral ClockFl4_main_clk >= 2 x (maximum Fsclk_out) †19.4.2.1.2. SPI Slave Bit-Rate ClockThe minimum frequency of
l4_main_clk depends on the operation of the slaveperipheral. If the slave device is receive only, the minimum frequency ofl4_main_clk is six times the maximum expected frequency of the bit-rate clock fromthe master device (sclk_in). The
sclk_in signal is double synchronized to thel4_main_clk domain, and then it is edge detected; this synchronization requiresthree
l4_main_clk periods. †Send Feedback
ControllerMNL-1100 | 2021.03.09If the slave device is transmit and receive, the minimum frequency of
l4_main_clkis 12 times the maximum expected frequency of the bit-rate clock from the masterdevice (sclk_in). This ensures that data on the master
rxd line is stable before themaster shift control logic captures the data. †The frequency ratio restrictions between the bit-rate clock
sclk_in and the SPI slaveperipheral clock are as follows: †••Slave (receive only): Fl4_main_clk >= 6 multiply (maximum Fsclk_in) †Slave: Fl4_main_clk >= 12 multiply (maximum Fsclk_in) †19.4.2.2. Transmit and Receive FIFO BuffersThere are two 16 or 32-bit FIFO buffers, a transmit FIFO buffer and a receive FIFObuffer, with a depth of 256. Data frames that are less than 16 or 32 bits in size mustbe right-justified when written into the transmit FIFO buffer. The data frame lengthdepends on the maximum transfer size. The shift control logic automatically right-justifies receive data in the receive FIFO buffer. †Each data entry in the FIFO buffers contains a single data frame. It is impossible tostore multiple data frames in a single FIFO buffer location; for example, you may notstore two 8-bit data frames in a single FIFO buffer location. If an 8-bit data frame isrequired, the upper 8-bits of the FIFO buffer entry are ignored or unused when theserial shifter transmits the data. †The transmit and receive FIFO buffers are cleared when the SPI controller is disabled(SPIENR=0) or transmit FIFO buffer is loaded by write commands to the SPI data register (DR).Data are popped (removed) from the transmit FIFO buffer by the shift control logicinto the transmit shift register. The transmit FIFO buffer generates a transmit FIFOempty interrupt request when the number of entries in the FIFO buffer is less than orequal to the FIFO buffer threshold value. The threshold value, set through the registerTXFTLR, determines the level of FIFO buffer entries at which an interrupt isgenerated. The threshold value allows you to provide early indication to the processorthat the transmit FIFO buffer is nearly empty. A Transmit FIFO Overflow Interrupt isgenerated if you attempt to write data into an already full transmit FIFO buffer. †Data are popped from the receive FIFO buffer by read commands to the SPI dataregister (DR). The receive FIFO buffer is loaded from the receive shift register by theshift control logic. The receive FIFO buffer generates a receive FIFO full interruptrequest when the number of entries in the FIFO buffer is greater than or equal to theFIFO buffer threshold value plus one. The threshold value, set through registerRXFTLR, determines the level of FIFO buffer entries at which an interrupt isgenerated. †The threshold value allows you to provide early indication to the processor that thereceive FIFO buffer is nearly full. A Receive FIFO Overrun Interrupt is generated whenthe receive shift logic attempts to load data into a completely full receive FIFO r, the newly received data are lost. A Receive FIFO Underflow Interrupt isgenerated if you attempt to read from an empty receive FIFO buffer. This alerts theprocessor that the read data are invalid. †Send Feedback
ControllerMNL-1100 | 2021.03.09Related InformationReset Manager on page 173For more information, refer to the Reset Manager chapter.19.4.2.3. SPI InterruptsThe SPI controller supports combined interrupt requests, which can be masked. Thecombined interrupt request is the ORed result of all other SPI interrupts aftermasking. All SPI interrupts have active-high polarity level. The SPI interrupts aredescribed as follows: †•Transmit FIFO Empty Interrupt – Set when the transmit FIFO buffer is equal to orbelow its threshold value and requires service to prevent an underrun. Thethreshold value, set through a software-programmable register, determines thelevel of transmit FIFO buffer entries at which an interrupt is generated. Thisinterrupt is cleared by hardware when data are written into the transmit FIFObuffer, bringing it over the threshold level. †Transmit FIFO Overflow Interrupt – Set when a master attempts to write data intothe transmit FIFO buffer after it has been completely filled. When set, new datawrites are discarded. This interrupt remains set until you read the transmit FIFOoverflow interrupt clear register (TXOICR). †Receive FIFO Full Interrupt – Set when the receive FIFO buffer is equal to or aboveits threshold value plus 1 and requires service to prevent an overflow. Thethreshold value, set through a software-programmable register, determines thelevel of receive FIFO buffer entries at which an interrupt is generated. Thisinterrupt is cleared by hardware when data are read from the receive FIFO buffer,bringing it below the threshold level. †Receive FIFO Overflow Interrupt – Set when the receive logic attempts to placedata into the receive FIFO buffer after it has been completely filled. When set,newly received data are discarded. This interrupt remains set until you read thereceive FIFO overflow interrupt clear register (RXOICR). †Receive FIFO Underflow Interrupt – Set when a system bus access attempts toread from the receive FIFO buffer when it is empty. When set, zeros are read backfrom the receive FIFO buffer. This interrupt remains set until you read the receiveFIFO underflow interrupt clear register (RXUICR). †Combined Interrupt Request – ORed result of all the above interrupt requests aftermasking. To mask this interrupt signal, you must mask all other SPI interruptrequests. †•••••Transmit FIFO Overflow, Transmit FIFO Empty, Receive FIFO Full, Receive FIFOUnderflow, and Receive FIFO Overflow interrupts can all be masked independently,using the Interrupt Mask Register (IMR). †19.4.3. Transfer ModesWhen transferring data on the serial bus, the SPI controller operates one of severalmodes. The transfer mode (TMOD) is set by writing to the TMOD field in controlregister 0 (CTRLR0).Note:
The transfer mode setting does not affect the duplex of the serial transfer.
TMOD isignored for Microwire transfers, which are controlled by the
MWCR register. †Send Feedback
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