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PM Tech

PMF512808A/PMF512816A/PMF412808A/PMF412816A

Document Title

4Gb (512M x 8 / 256M x 16) DDRIII SDRAM A Die Datasheet

Revision History

Revision Date Page

0.1 December, 2011 - Preliminary

0.2 February, 2012 - R02 release

1.0 April, 2012 - Official release

Notes

This document is a general product description and subject to change without notice.

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PM Tech

PMF512808A/PMF512816A/PMF412808A/PMF412816A

4GBIT DDRIII DRAM

Features

Density: 4G bits

1.35V -0.0675V/+0.1V & 1.5V ± 0.075V

8 Internal memory banks (BA0- BA2)

Differential clock input (CK, /CK)

Programmable CAS Latency:

5, 6, 7, 8, 9, 10, 11, 12,13

CAS WRITE Latency (CWL): 5,6,7,8,9

POSTED CAS ADDITIVE Programmable

Additive Latency: 0, CL-1, CL-2 clock

Programmable Sequential / Interleave Burst Type

Programmable Burst Length: 8, 4 with burst chop

8n-bit prefetch architecture

Output Driver Impedance Control

Differential bidirectional data strobe

Internal(self) calibration:Internal self calibration

OCD Calibration

Through ZQ pin (RZQ:240 ohm±1%)

Dynamic ODT (Rtt_Nom & Rtt_WR)

Automatic Self-Refresh (ASR)

Self refresh mode and Partial array self refresh

Thermal sensor on die using MPR

T case=95°C (with 2X refresh);

T case=85°C (with 1X refresh)

SSTL_15 JEDEC standard compatible

inputs/outputs interface

RoHS compliance and Halogen free

Package:

- 78ball BGA for x8 component

- 96ball BGA for x16 component

Speed DDR3(L)-1066 DDR3(L)-1333 DDR3(L)-1600 DDR3(L)-1866

Unit

9-9-9 11-11-11 12-12-12 CL-RCD-RP 7-7-7

Parameter Min Max Min Max Min Max Min Max

Clock Frequency 300 533 300 667 300 800 300 933 MHz

t

RCD

t

RP

t

RC

t

RAS

13.125 - 13.125

13.125 - 13.125

- 13.125

- 13.125

- 12.84 - ns

- 12.84 - ns

50.625 - 49.5 - 48.75 - 47.08 - ns

37.5 70K 36 70K 35 70K 34 70K ns

*The timing specification of high speed bin is backward compatible with low speed bin

Rev 1.0

2

April 2012